高性能全搜索可变块运动估计的VLSI设计

VLSI design of full search variable-block size matching motion estimation processer

给出了一种用于H.264全搜索可变块匹配算法的运动估计电路的改进结构,并完成了VLSI设计的仿真验证。在传统脉动阵列,全流水线设计的基础上,通过引入片内Cache,增加输入端口,大大减少传统方式下对延迟寄存器的依赖,进一步降低了功耗。仿真实验以CIF图像(352×288)为例进行结构验证,证明设计能实时处理H.264格式标准下的视频序列。

An improved architecture for H.264 by full searchvariable-block size matching motion estimation processer was proposed and the simulation verification of VLSI design was implemented in this paper.Based on traditional systolic array and full pipe line architecture,the new structure introduced on-chip cache and increased data inputs,which largely reduced dependence on delay registers,and also largely reduced power consumption.Simulation by CIF（352×288） video sequences proved the capability of processing H.264 formatted video sequences.