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X-DSP浮点乘法器的设计与实现 被引量：1

Design and implementation of float point multiplier in X-DSP
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摘要 为了满足高性能X-DSP浮点乘法器的性能、功耗、面积要求,研究分析了X型DSP总体结构和浮点乘法器指令特点,采用Booth2编码算法和4∶2压缩树形结构,使用4级流水线结构设计实现了一款高性能低功耗浮点乘法器。使用逻辑综合工具Design Compiler,采用第三方公司0.13μmCMOS工艺库,对所设计的乘法器进行了综合,其结果为工作频率500MHz,面积67529.36μm2,功耗22.3424mW。 In order to meet the requirements on performance, power, area of float point multiplier in X-DSP, the architecture of X-DSP was studied, and the characteristics of all the instructions related to its float point multiplier were analyzed. A high-performance and low-power float point multiplier, which used Booth 2 encoding algorithm and 4∶2 compress tree structure and adopt a 4-stage pipeline structure, was designed and implemented. The floating-point multiplier was also synthesized by using design compiler with 0.13 μm CMOS technique of a third-party company. The results show that the frequency is 500 MHz, the area of the circuit is 67529.36 μm2, and the total circuit power consumption is 22.3424 mW.
作者 彭元喜 杨洪杰 谢刚
机构地区 国防科学技术大学计算机学院
出处 《计算机应用》 CSCD 北大核心 2010年第11期3121-3125,3133,共6页 journal of Computer Applications
基金 国家自然科学基金资助项目(60676010) 国家863计划项目(2007AA01Z108) 教育部长江学者和创新团队发展计划项目
关键词 4∶2压缩树 布斯算法 IEEE-754 浮点乘法器 数字信号处理器 4∶2 compression tree Booth algorithm IEEE-754 floating-point multiplier Digital Signal Processor （DSP）
分类号 TP301.6 [自动化与计算机技术—计算机系统结构] TP342.2 [自动化与计算机技术—计算机系统结构]
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参考文献11

  • 1OBERMAN S F. Design issues in high performance floating point arithmetic units [ D]. Stanford: Stanford University, 1997.
  • 2BOOTH A D. A signed binary multiplication technique [ J]. Quaterly Journal of Mechanics and Applied Mathematic, 1951, 4(2) : 236 - 240.
  • 3MA G K, TAYLOR F J. Multiplier policies for digital signal processing [ J]. IEEE ASSP Magazine, 1990, 7(1) : 6 - 20.
  • 4OHKUBO N, SUZUKI M, HINBO T. A 4.4 ns CMOS 54 × 54-b multiplier using pass-transistor multiplexer [ J]. IEEE Journal of Solid-State Circuits, 1995, 30(3) : 251 -256.
  • 5MAKINO I H, NAKASE Y, SUZUKI H. An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture [ J]. IEEE Journal of Solid-State Circuits, 1996, 31(6) : 773 -783.
  • 6INOUE A, OHE R, KASHIWAKURA S, et al. A 4. lns compact 54 × 54-bit multiplier utilizing sign select Booth encoders [ C ]// IEEE Intemational Conference on Solid State Circuits. Washington, DC: IEEE, 1997:416-417.
  • 7HAGIHARA Y, INUI S, YOSHIKAWA A, et al. A 0.25 μm CMOS 54 × 54-bit multiplier [ C]// IEEE International Conference on Solid-State Circuits. Washington, DC: IEEE, 1998: 296- 297.
  • 8ITOH N, NAEMURA Y, MAKINO H, et al. A 600 MHz 54 × 54- bit multiplier with rectangular-styled Wallace tree [ J]. IEEE Journal of Solid-State Circuits, 2001, 36(2) 249-257.
  • 9CHO KI-SEON, PARK JONG-ON, HONG JIN-SEOK, et al. A 54 ×54-bit radix-4 multiplier based on modifid booth algorithm [ C]//Proceedings of the 13th ACM Great Lakes symposium on VLSI. New York: ACM Press, 2003:233-237.
  • 10黄宁,朱恩.32位高性能浮点乘法器芯片设计研究[J].电子工程师,2008,34(1):57-59. 被引量：1

二级参考文献16

  • 1刘国栋,陈伯孝,陈多芳.FFT处理器的FPGA设计[J].航空计算技术,2004,34(3):101-104. 被引量：12
  • 2吴金,应征.高速浮点乘法器设计[J].电路与系统学报,2005,10(6):6-11. 被引量：7
  • 3BOOTH A D.A signed binary multiplication technique[J].Quarterly Journal of Mechanics and Applied Mathematics,1951,4(2):236-240.
  • 4WALLACE C S.A suggestion for a fast multiplier[J].IEEE J Trans Electron Compute,1964,13(1):14-17.
  • 5PRASAD K,PARHI K K.Low-power 4-2 and 5-2 compressors[J].The 35th Asilomar Conf on Signals Systems and Computers,2001,1:129-133.
  • 6WANG Z,JULLIEN G A,MILLER W C.A new design technique for column compression multipliers[J].IEEE Trans Comput,1995,44(1):962-970.
  • 7GOTO G,INOUE A,OHE R.A 4.1-ns compact 54×54-b multiplier utilizing sign-select booth encoders[J].IEEE J of Solid-State Circuits,1997,32(11):1676-1681.
  • 8VEERAMACHANENI S,KRISHANA K,AVINASH L.Novel architectures for high-speed and low-power 3-2,4-2 and 5-2 compressors[C]//IEEE Int Conf on VLSI Design.India,2007.
  • 9HWARD G M,MOKRIAN P,AHMADI M.Power and delay analysis of 4:2 compressor Cell[C]//IEEE Int Symp on ISCAS.Country of Publication,USA,2005,4:3559-3562.
  • 10韦恩·沃尔夫.现代VLSI设计:系统芯片设计[M].张欣,等,译.北京:科学出版社,2004.

共引文献1

同被引文献8

  • 1WANG X, ZHANG Y, WANG F, et al. A configurable floating- point discrete Hilbert transform processor for accelerating the calcu- lation of fiher in Katsevich formula [ J]. WSEAS Transactions on Communications, 2012, 11 (11) : 395 - 404.
  • 2MONTOYE R K, HOKENEK E, RUNYON S L. Design of the IBM RISC System/6000 floating-point execution unit [ J]. IBM Journal of Research and Development, 1990, 34(1): 59-70.
  • 3LANG T, BRUGUERA J D. Floating-point fused multiply-add with reduced latency [ J]. IEEE Transactions on Computers, 2004, 53 (8) : 988 - 1003.
  • 4LANG T, BRUGUERA J D. Floating-point fused muhiply-add: re- duced latency for floating-point addition [ C]// ARITH '05: Pro- ceedings of the 17th IEEE Symposium on Computer Arithmetie. Washington, DC: IEEE Computer Soeiety, 2005:42-51.
  • 5RUBINFIELD L P. A proof of the modified Booth's algorithm for multiplication [ J]. IEEE Transactions on Computer, 1975, 24 (10): 1014-1015.
  • 6方维,孙广中,吴超,陈国良.一种三维快速傅里叶变换并行算法[J].计算机研究与发展,2011,48(3):440-446. 被引量：9
  • 7何军,黄永勤,朱英.分离通路浮点乘加器设计与实现[J].计算机科学,2013,40(8):28-33. 被引量：1
  • 8张拥军,陈艇.基于软件无线电的并行多输入多输出均衡技术[J].计算机应用,2015,35(4):1179-1184. 被引量：3

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计算机应用
2010年 第11期

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