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高性能桶形整数加法器的设计 被引量:1

Design of high performance barrel integer adder
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摘要 为了提高加法器的运算速度,提出了一种新型并行整数加法算法——桶形整数加法算法。该加法器以半加器为基础,将并行与迭代反馈思想相结合,根据每轮迭代后进位链的值判断是否已经累加结束,可以在保持低功耗的同时提高运算速度。仿真结果表明,该桶形整数加法器在面积少量增加的基础上,速度提高明显。 To accelerate the adder, a new parallel integer addition algorithm — carry barrel adder algorithm was proposed. The adder applied half-adder, combining parallel and iterative feedback ideas, judging the completion of a summation according to the value of the carry chain produced after each round of iteration, which can maintain the acceleration of calculation on low power consumption. The simulation results show that the proposed design of the barrel integer adder can accelerate prominently in slight augmentation of areas.
作者 张镇 冯婧
出处 《计算机应用》 CSCD 北大核心 2010年第11期3138-3140,共3页 journal of Computer Applications
基金 国家自然科学基金资助项目(60672041)
关键词 半加器 VERILOG 整数加法器 现场可编程门阵列 half-adder Verilog integer adder Field-Programmable Gate Array (FPGA)
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参考文献8

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