高速嵌入式系统中电源噪声抑制方法

Power Bus Noise Suppression in High Speed Embedded Systems

根据平面腔体谐振模型理论推导出高速嵌入式电路电源平面对阻抗函数关系式,分析了电源平面对的谐振特性与PCB板材、介质层厚度以及导体平面的电导率之间的关系,得出可通过减小介质层厚度、使用高介电常数的介质材料以及增加介质损耗等3种方法来抑制电源平面对的谐振效应,并使用全波仿真方法验证了可行性。从时域仿真了高速电路中的噪声传播与电源平面谐振的相互关系,结果表明,通过抑制电源平面对谐振阻抗可将电源噪声减小至原有结构的15%,从而有效提高系统的电源完整性。

The analytic expression of power plane pair impedance is proposed based on the cavity model resonances, the relation functions among power plane pair resonant impedance, PCB material, the plane spacing and conductivity of conductive are deducted. Decreasing the space of the planes, using high permittivity and high loss tangent insulation material are three basic methods to suppress impedance at resonance. The methods are verified based on full wave FEM simulation. The relationship between the noise propagation and plane pair impedance is illustrated through the time domain simulation, and the results show that the power noise is reduced over 85 % compared with conventional power plane by suppressing the impedance at resonance and power integrity is dramatically increased.