摘要
通过对相位插值器电路进行建模分析,得到了相位插值器的线性度与输入信号之间相位差、输入信号上升时间和输出节点时间常数的关系。根据分析得到的结论,提出了一种新型的应用于连续数据速率时钟数据恢复电路的相位插值器,通过在相位插值器之前插入延时可控的缓冲器,使其输入信号的上升时间可以跟踪数据速率的改变,在保证线性度的同时,降低电路的噪声敏感度和功耗。芯片采用Charterd 0.13μm低功耗1.5/3.3 V工艺流片验证,面积为0.02 mm2,数据速率3.125 Gb/s时,功耗为8.5 mW。
An abstract model was setup for the phase interpolator,and precise analysis was performed using this model.The influence of input clock signals,the input phase spacing and output signal slew rate on slope were derived from the analysis.According to the conclusions,a phase interpolator was designed for applications of continuous-rate clock and data recovery circuits.The circuit is fabricated in Charterd 0.13 μm low power 1.5/3.3 V technology,the active area is 0.02 mm2,and the power consumption is 8.5 mW with 3.3 V power supply when operated at 3.125 Gb/s.
出处
《半导体技术》
CAS
CSCD
北大核心
2010年第10期999-1002,共4页
Semiconductor Technology
基金
国家科技重大专项资助项目(2009ZX03007-002-03)
