通用型I^2C总线的IP设计与验证

THE IP DESIGN AND VERIFICATION OF GENERAL I～2C BUS

集成电路设计已经步入SoC时代,而IP设计和IP复用技术是SoC设计的重要支持。本文以通用型I2C总线为例,介绍了典型的数字IP的设计与功能验证实现。这里采用HDL-Verilog语言进行自顶向下的设计,通过搭建验证平台、提取功能验证点完成软核的功能验证,并且运用Perl开发了脚本程序以提高验证效率。

Integrated circuits design has entered the age of SoC,both IP design and IP reuse are great supports for SoC design nowadays.This paper takes general used I2C bus as an example to introduce the implementation of typical digital IP designing and soft IP＇s functional verification.Top-down design method by using HDL-verilog is adopted here,function verification of soft IP is completed via constructing testbench as well as extracting function testcases.Perl language scripts programs are also developed in order to improve the efficiency of function verification.