一种电子系统认证芯片的物理设计

The Physical Design of An Electronic System Certification Chip

为了防止电子产品被非法克隆复制,本文对一款利用系统认证原理对电子系统进行保护的芯片FD310S进行了物理设计。该系统认证芯片是基于华虹NEC 0.35μm三层金属工艺,采用SoC Encounter时序收敛流程进行设计,进行了包括布图规划、时序驱动布局、静态时序分析和优化、时钟树综合和时序驱动布线等步骤,最终实现了时序收敛;并且在Virtuoso环境中对其中一个形状特殊的复用I/O Pad进行了电源环的连接。该设计成功通过了设计规则检查(DRC)和版图与原理图一致性检查(LVS)。

In order to prevent illegally cloning of electronic products, the physical design of a system certification chip FD310S which protected the electronic system is introduced. Based on Hua Hong NEC 0.35 um IP3M technology, the timing closure design flow of Soc Encounter is used, analysis and optimization, clock tree synthesis and including floorplan, timing-driven placement, static timing timing-driven routing. After achieving timing closure, the connection between a special shape reused I/O pad and the power rings of whole chip are created in Virtuoso environment. The design has successfully passed the DRC （ Design Rule Check ） and LVS （ Layout Versus Schematic ）.