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Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip(MP-SoC) 被引量:3

Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip(MP-SoC)
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摘要 This paper evaluates the Triplet Based Architecture,TriBA-a new idea in chip multiprocessor architectures and a class of Direct Interconnection Network(DIN).TriBA consists of a 2D grid of small,programmable processing units,each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized.Any communication model can be well characterized by locality properties and,any topology has its intrinsic,structural,locality characteristics.We propose a new criterion in performance evaluation that is based on the concept of locality in an interconnection network,the "lower layer complete connect".Our proposed criterion depicts how completely a processing node is connected to all its neighbors.TriBA is compared with 2D Mesh and Binary Tree as static interconnection network.The comparison/evaluation is enumerated from three orthogonal view points,viz.,computational speed,physical layout and cost.Our analysis concludes that TriBA is computationally efficient interconnection strategy that exploits group locality in processing nodes. This paper evaluates the Triplet Based Architecture, TriBA - a new idea in chip multiprocessor architectures and a class of Direct Interconnection Network (DIN). TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized. Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. We propose a new criterion in performance evaluation that is based on the concept of locality in an interconnection network, the "lower layer complete connect". Our proposed criterion depicts how completely a processing node is connected to all its neighbors. TriBA is compared with 2D Mesh and Binary Tree as static interconnection network. The comparison / evaluation is enumerated from three orthogonal view points, viz., computational speed, physical layout and cost. Our analysis concludes that TriBA is computationally efficient interconnection strategy that exploits group locality in processing nodes.
出处 《Chinese Science Bulletin》 SCIE EI CAS 2010年第29期3363-3371,共9页
基金 supported by the National Natural Science Foundation of China (60973010) the Doctoral Fund of Ministry of Education of China (200800071005)
关键词 互连网络 系统级芯片 拓扑结构 多处理器 计算效率 局部性 SOC MP multiprocessor, locality, interconnection network, VLSI layout, performance evaluation
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  • 1Jayanta B, Ekaterina T, Magdy S A. Validating power architecture topology-based Mpsoc through executable specifications. IEEE Trans VLSI, 2008, 16:388-396.
  • 2Jerraya A A, Bouchhima A, Petrot F. Programming models and Hw-sw interfaces abstraction for multi-processor Soc. In: Ellen S, ed. Proceedings of the 43rd ACM/IEEE Design Automation Conference, 2006 Jul 24-28, San Francisco: Association for Computer Machinery Inc. Press, 2006. 280-285.
  • 3Magarshack P, Paulin P G. System-on-chip beyond the nanometer wall. In: Fix L, Getreu I, Lavangoa L, eds. Proceedings of the 40th ACM/IEEE Design Automation Conference, 2003 Jun 2-6, Anaheim California: Association for Computer Machinery Inc. Press, 2003. 419424.
  • 4Jerraya A A, Wolf W. Multiprocessor Systems-on-Chip. San Francisco: Elsevier Morgan Kaufmann, 2005.431-462.
  • 5Pande P P, Grecu C, Jones M, et al. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. Computer, 2005, 54:1025-1040.
  • 6Rakesh K, Victor Z, Dean M T. Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling. In: Bob W, ed. Proceedings of the 32nd International Symposium on Computer Architecture, 2005 Jun 4-8, Madison Wisconsin: IEEE Computer Society, 2005.408-419.
  • 7Shi F, Ji W X, Qiao B J, et al. A triplet based computer architecture supporting parallel object computing. In: Proceedings of 18th IEEE International Conference on Application-specific Systems, Architectures and Processors, 2007 Jul 9-11, Montreal Canada: IEEE Press, 2007. 192-197.
  • 8Thompson C D. Generalized connection networks for parallel processor intercommunication. IEEE Trans Compu, 1978, c-27: 1119-1125.
  • 9Horowitz M, Dally B. How scaling will change processor architecture. In Laura C F, Mandana A, Arvin G, eds. Proceedings of the IEEE International Solid State Circuits Conference, 2004 Feb 15-19, San Francisco: S3 Digital Publishing Inc., 2004. 132-133.
  • 10Lupu C, Niculiu T. Interconnection locality and group locality. In: Ljiljana M, Miroslav L, Aleksandar N, eds. Proceedings of The International Conference on computer as a tool- EUROCON, 2005 Nov 21-24, Belgrade Serbia and Montenegro: IEEE and University of Belgrade, 2005.656-659.

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