基于3GPP标准的Turbo码译码器设计与实现

Design and Implementation of Turbo Decoder Based on 3GPP

文中针对3GPP标准的Turbo码的性能进行仿真分析,基于课题的要求,根据性能和FPGA硬件实现复杂度提出了一种新颖的译码器方案。本方案采用在分量译码器计算前向递推的数据时,只对前向递推量进行存储,在后续过程中将同时计算出的分支度量和后向递推量结合已经存储的前向递推量直接更新信息比特的似然信息和外信息,节省了硬件存储器资源,提高了译码吞吐量,根据硬件系统时钟可推算出大致的译码吞吐量,达到课题要求。本方案的思想同样可推广应用于其他标准的Turbo码译码器。

Analyse the performance of Turbo code based on 3GPP protocol through simulation,in accordance with the requirements of the subject,a novel decoder scheme is proposed considering the performance and the implementation complexity of FPGA.This scheme only stores the forward path metrics in the process of computing itself,in the next round it computes the branch metrics and backward path metrics simultaneously,which are combined with the forward path metrics stored in the first round immediately in the purpose of updating LLR and extrinsic information of the information bits.This scheme saves lots of hardware memory resources and improves the throughput of decoder which can be estimated according to the system clock.The requirement of the subject can be achieved using this scheme,and this scheme can also be used in the other Turbo decoders of different standards.