摘要
插值滤波器性能直接影响到全数字接收机的误码率,设计性能良好且易于硬件实现的插值滤波器是设计全数字接收机的关键.在对已有的拉格朗日立方插值滤波器Farrow结构进行分析和研究的基础上,使用了并行处理技术来提高滤波器的速度,并对该算法结构进行了仿真,在FPGA上实现.分析结果表明,改进后的结构有更快的运行速度和更低的功耗.
The performance of interpolation filter has a direct impact on the bit error rate of all digital receiver. It is the key to all-digital receiver that design a good performance of the interpolation filter. The analysis and research are based on the existing Farrow structure of Lagrange interpolation filter. The parallel processing technology are used to improve the speed of filter. We have simulated and realized the structures for FPGA. The results show that the structure has faster operational rate and lower energy consumption.
出处
《微电子学与计算机》
CSCD
北大核心
2010年第11期82-85,90,共5页
Microelectronics & Computer
基金
国家自然科学基金项目(60466047)
