16位音频sigma-delta调制器设计(英文)

Design of a 16-bit sigma-delta modulator for digital audio signal processing

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摘要针对数字音频领域16bit精度、20kHz带宽的设计要求,以0.18μmCMOS工艺设计二阶单环的一位sigma-delta调制器,过采样率达256,采样频率达10.24MHz.调制器采用了全差分结构,由基于开关电容的积分器、时钟产生器及比较器等组成.仿真结果显示,该调制器的信噪失真比达94dB,动态范围达99dB.在1.8V电源电压下,整个系统的功耗为7.6mW. With the design requirements of 16-bit resolution and 20 kHz bandwidth for digital audio field,a second-order single-loop 1 bit sigma-delta modulator with an oversampling rate of 256 and a sampling frequency of 10.24 MHz was implemented in a 0.18 μm CMOS process.The modulator is fully differential.It consists of a switch capacitor based integrator,a clock generator and a comparator.Simulation results show that the signal to noise distortion ratio（SNDR）and the dynamic range（DR）of the implemented modulator reach 94 dB and 99 dB,respectively.The sigma-delta modulator operates with a supply voltage of 1.8 V,and consumes 7.6 mW of power.

作者马芝李琰愈航姜来纪震

机构地区深圳IC基地管理中心深圳市嵌入式系统设计重点实验室深圳大学计算机与软件学院

出处《深圳大学学报（理工版）》 EI CAS 北大核心 2010年第4期425-427,共3页 Journal of Shenzhen University(Science and Engineering)

基金 supported by the National Natural Science Foundation ofChina(60901016)~~

关键词集成电路技术数字音频 SIGMA-DELTA调制器开关电容动态范围信噪失真比 IC technology digital audio sigma-delta modulator switched capacitor dynamic range signal-to-noise distortion ratio

分类号 TN792 [电子电信—电路与系统] TN43 [电子电信—微电子学与固体电子学]

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深圳大学学报（理工版）

2010年第4期

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16位音频sigma-delta调制器设计(英文)

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