一种使用调控器针对数据通路的综合功能的时间扩展模型生成方法(英文)

A comprehensive functional time expansion model generation method for datapaths using controllers

一些超大规模集成电路(VLSI)近来通过行为描述已在高层次被设计.行为合成可以将行为描述变换成由控制器和数据通路组成的寄存器传输层电路.数据通路的控制信号线输入序列和状态信号线输出序列从控制器提取.作者提出一种生成综合功能时间扩展模型的方法,其中提取的信息作为约束被加入.在常规的贯序测试生成方法中使用时间模型只有结构信息,因为对于实际的贯序电路的搜索空间相当庞大,所以在合理时间内很难达到高排错效率.在使用来自功能验证模块的功能时间扩展模型的贯序测试生成方法中,因为所有的功能行为不可能全被覆盖,所以很难提高排错效率.由于作者提出的方法可以覆盖所有的功能行为,所以与常规的方法相比可以实现在合理时间内的高排错效率.所提出的测试生成方法被用于除法器电路.实验数据显示了在16s内排错覆盖率达到了100%.

Some very large-scale integrated circuits （VLSI） have been recently designed at high-level by behavioral descriptions.Behavioral synthesis can transform behavioral descriptions to register transfer level circuits that consist of a controller and a datapath.In this paper,sequential circuits that consist of a controller and datapath are the focus.Latency,the input sequence for control signal lines,and the output sequence for status signal lines of datapaths are extracted from controllers.We propose a generation method of comprehensive functional time expansion models in which the extracted information is incorporated as constraints.In a conventional sequential test generation method using time expansion models with only structural information,because the search space is extremely huge for practical sequential circuits,it is difficult to achieve high fault efficiency with reasonable time.In a sequential test generation method using functional time expansion models from functional verification patterns,because all the functional behavior cannot be covered,it is difficult to improve fault efficiency.Because the proposed method can cover all the functional behavior,it is possible to achieve high fault efficiency with reasonable time compared to conventional methods.The proposed test generation method is applied to a divider circuit.The experimental results show that the fault efficiency is achieved to 100% with 16 second.