期刊文献+

一种基于开关逻辑结构的低功耗SAR ADC的设计 被引量:3

A Low Power Successive Approximation Register Analog-to-Digital Converter Based on Switch Logic Architecture
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摘要 设计并实现了一款10位逐次逼近型模数转换器,该电路采用了改进型开关逻辑结构降低了开关的动作频率,提高了数模转换器的线性度,同时降低了模数转换器的功耗.仿真结果表明,该模数转换器在Chartered 0.35μm 2P4M工艺下实现了10位精度,转换速率为250 kHz,信噪比大于60 dB,功耗小于2 mW.流片后测试结果显示芯片达到设计指标要求,平均功耗为1.97 mW. A 10-bit successive approximation register analog-to-digital converter was designed and implemented. An improved structure was adopted for the switch array in the digital-to-analog converter in order to reduce switch operation, which improved the linearity of digital-to-analog converter and reduced the total power consumption of the analog-tu-digital converter as well. The circuit simulation results showed that the digital data output with a precision of ten figures had a conversion rate of 250 kHz in the Chartered 0.35 μm 2P4M process. The analog-to-digital converter had a signal-to-noise ratio larger than 60 dB and the total power dissipation was less than 2 roW. The circuit was fabricated and the measured results showed the design specification met the requirement, and the average power consumption was 1.97 mW.
出处 《天津大学学报》 EI CAS CSCD 北大核心 2010年第10期879-883,共5页 Journal of Tianjin University(Science and Technology)
基金 天津市科技支撑计划资助项目(08ZCKFGX00200)
关键词 低功耗 逐次逼近型模数转换器 开关逻辑 low power successive approximation register analog-to-digital converter switch logic
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参考文献14

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共引文献1

同被引文献17

  • 1周文婷,李章全.SAR A/D转换器中电容失配问题的分析[J].微电子学,2007,37(2):199-203. 被引量:13
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