源、漏到栅距离对次亚微米ggNMOS ESD保护电路鲁棒性的影响

Effect of distances from source or drain to the gate on the robustness of sub-micron ggNMOS ESD protection circuit

基于对静电放电(electrostatic discharge,ESD)应力下高电压、大电流特性的研究,本文通过优化晶格自加热漂移-扩散模型和热力学模型,并应用优化模型建立了全新的0.6μm CSMC6S06DPDM-CT02CMOS工艺下栅接地NMOS(gate grounded NMOS,ggNMOS)ESD保护电路3D模型,对所建模型中漏接触孔到栅距离(drain contact togate spacing,DCGS)与源接触孔到栅距离(source contact to gate spacing,SCGS)对保护电路鲁棒性指标--开启电压、击穿电压、自热峰值等参数的影响进行了系统研究.仿真结果表明,DCGS和SCGS的改变对保护电路的开启电压和热平衡没有影响,而DCGS比起SCGS对保护电路的击穿电压和器件的自热峰值敏感度更高,但持续增大DCGS和SCGS并不能单调提升保护电路的击穿电压值以及降低器件的自热峰值,因此不宜单一通过增大DCGS和SCGS的方式来改善ESD保护电路的鲁棒性.仿真结果与0.5μm和0.6μm CMOS工艺流片的传输线脉冲(transmission line pulse,TLP)测试结果对比显示,本文建立模型的仿真结果较好地反映了保护电路在ESD条件下的电、热特性趋势,其结论与测试结果符合.本文的研究结果为次亚微米ggNMOS ESD保护电路版图设计中的参数选取提供了依据.

In this paper,based on the research of the features about high voltage and high current under electrostatic discharge （ESD）,the new 3D model of 0.6 μm gate-grounded NMOS（ggNMOS） ESD protection circuit with CSMC 6S06DPDMCT02 CMOS technology have been derived from the optimization of lattice self-heating drift/diffusion model and its thermal model;systematic study about the effect of drain contact to gate spacing（DCGS） and the source contact to gate spacing （SCGS）on the relative protection circuit robustness index（turn-on voltage,breakdown voltage,self-heating peak,etc）have been done based on this model.The simulation results show that turn-on voltage and thermal balance are not influenced by the change of DCGS and SCGS,and compared to SCGS,DCGS is more sensitive to the breakdown voltage and the selfheating peak value of protection circuit.To improve the robustness of ESD protection circuit,it is not appropriate to monotonic increase the DCGS and SCGS for the reason that the breakdown voltage cannot be increased and the self-heating peak value of devices cannot be reduced by increasing DCGS and SCGS continuously.Compared to the TLP test results of 0.5 μm and 0.6 μm CMOS,a better reflection about the trend of electrical and heating features is derived from the simulation results,and the conclusions and test results are fully consistent.The reference for sub-micrometer ggNMOS ESD protection circuit layout parameter can be provided by the study.