摘要
提出了一种基于FPGA的小数分频实现方法。介绍了现有分频方法的局限性,提出一种新的基于两级计数器的分频实现方法,给出该方法的设计原理以及实现框图,利用软件对电路进行仿真,由仿真结果可以看出该方法可有效实现输入信号频率的小数调整,最后分析了方法的优缺点及其应用领域。实验结果表明,设计方法能够高精度地完成对信号频率的微调,并且频率转换时间被缩短到2.56μs。
This paper presents a method for realizing the decimal frequency divider based on FPGA, introduces the limitation of the current frequency dividing design in brief, and a new method based on two grades＇ counters for implementing the decimal frequency divider is given. The principle of the design and the block diagram of the realization are also presented in this paper. Through simulated by software, this method is proved to be able to effectively implement the adjustment of the fraction of the input signal frequency. The advantages and disadvantages of this method are analyzed. The results show that this method can complete the slight adjustment of the signal frequecy,and the frequency switching time has been reduced to 2.56 μs.
出处
《电子技术应用》
北大核心
2010年第11期99-101,共3页
Application of Electronic Technique
基金
中央高校基本科研业务费专项资金资助(JY10000904015)
关键词
FPGA
小数分频
信号频率的微调
FPGA
the decimal frequency divider
the slight adjustment of the signal frequecy
