JPEG-LS多路并行译码的FPGA实现

FPGA implementation of JPEG-LS multi-channel parallel decode

提出了一种基于FPGA的JPEG-LS的多路并行译码系统,运用VHDL语言实现,以提高图像的译码速度。系统主要分为检测模块、译码模块和码流分配模块三部分。在检测模块中提取和去除头文件的图像信息,译码模块则根据算法对图像数据进行恢复,码流分配模块为多路并行算法的关键,利用流水线结构的思路采用乒乓操作将码流从检测模块传送到外部RAM。在译码时采用同样的方法将数据送入多个译码模块进行译码。

In this paper,a JPEG-LS multi-channel parallel decode system is designed base on FPGA,which implemented with VHDL and speed up the decoding of picture.The system is consisted of detect module,decode module and code-stream assignment module.Detect module extracts and remove the information of the picture.The decode module reconstruct image data.Code-stream assignment is the key point of the parallel algorithm,which adopts pipeline method,sends the code-stream from detect module to external RAM by ping-pang operation.And send the image data which saved in external RAM to multi-decode module in the same way.