一种高速跳频接收机的改进设计方案

An improved design of high-speed frequency hopping receiver

提出了一种新的利用接收机前端双多锁相环(PLL)和基带直接数字频率合成(DDS)共同实现高速跳频的设计方案,根据系统的特点确定动态范围、发射功率、接收灵敏度等关键指标,进行了高速跳频制导接收机的总体方案、射频前端和基带基本算法框架设计,实现了76000跳/s的跳频速率,减小了接收机的体积,同时降低了功耗。理论分析和测试结果表明,接收机达到了较高的性能。

A high speed frequency hopping receiver is proposed,which utilizes the front-end pair of multi-phase-locked loop（PLL） and baseband direct digital synthesizer（DDS）.The novel scheme achieves a 76 000 jump/s frequency hopping rate and decreases the volume of receiver,while reducing the power consumption.According to the characteristics of the system for dynamic range,transmit power,receive sensitivity and other key indicators,the high-speed frequency hopping receiver overall program guidance,the RF front-end and baseband basic algorithm framework are designed.Theoretical analysis and test results show that the proposed receiver can achieves high performance.