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半导体封装生产线工艺流程分析 被引量:3

Analysis of in Semiconductor Packaging Production Line
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摘要 本文介绍了半导体生产线后道封装流程,并对相关设备的自动化程度进行分析。 In this paper, the technical process of semiconductor packaging production line is discussed,and the automation degree of relative equipments is analyzed.
出处 《科技广场》 2010年第8期147-149,共3页 Science Mosaic
基金 住房和城乡建设部项目(2010-K9-49)
关键词 半导体 封装生产线 自动化设备 Semiconductor Packaging Production Line Automated Equipment
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  • 1李莉,乔非,姜桦,吴启迪.半导体生产线动态调度方法研究[J].计算机集成制造系统,2004,10(8):949-954. 被引量:14
  • 2Yongcai WANG Qianchuan ZHAO Dazhong ZHENG.BOTTLENECKS IN PRODUCTION NETWORKS: AN OVERVIEW[J].Journal of Systems Science and Systems Engineering,2005,14(3):347-363. 被引量:2
  • 3张怀,江志斌,郭乘涛.面向瓶颈的半导体晶圆制造系统派工策略及参数优化[J].上海交通大学学报,2007,41(8):1252-1257. 被引量:10
  • 4UZSOY R, LEE C Y, MARTIN-VEGA L A. A review of production planning and scheduling models in the semiconductor industry Part Ⅱ: Shop-floor control [J]. IIE Transactions, 1994,26(5) :44-55.
  • 5LIU Huiran, JIANG Zhibin, FUNG R Y K. The infrastructure of the timed EOPNs based multiple objective real-time scheduling system for 300mm wafer fab[J]. International Journal of Production Research, 2007, 45(21) :5017-5056.
  • 6KNESSL C, TIGER C. Asymptotic approximations and bottleneck analysis in product form queueing networks with large populations [J]. Performance Evaluation, 1998, 33(4):219-248.
  • 7POLLETT P K. Modelling congestion in closed queueing networks [J]. International Transactions in Operations Research, 2000, 7(4/5) :319-330.
  • 8KUO C T, I.IM J T, MEEKOV S M. Bottlenecks in serial production lines:a system-theoretic approach [J]. Mathematical Problems in Engineering, 1996,2(3):2:33-276.
  • 9CHIANG S Y, KUO C T, MEEKOV S M. Bottlenecks in Markovian production lines: a systems approach [J]. IEEE Transactions on Robotics and Automation, 1998, 14 (2) : 352-359.
  • 10CHIANG S Y, KUO C T, MEEKOV S M. C-bottlenecks in serial production lines: identification and application [C]// Proceedings of the 38th IEEE Conference on Decision and Control. Washington, D. C. , USA : IEEE, 1999 :456-461.

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  • 1鲜飞.微电子封装技术的发展趋势[J].电子元器件应用,2004,6(8):41-44. 被引量:3
  • 2胡雅琴,何桢.论六西格玛管理的本质属性[J].科学学与科学技术管理,2004,25(10):137-139. 被引量:70
  • 3科兹纳.项目管理[M].北京:电子工业出版社,2006.
  • 4FurberS.ARMSystem-on-ChipArchitecture(ARMSoC体系结构)[M].田泽,于敦山,译.台北:五南图书出版公司,2003.
  • 5田泽.SoC设计与测试[M].北京:航空工业出版社,2003.
  • 6项目管理协会.Projectmanagementinstitute[M].北京:电子工业出版社.2009.
  • 7Hodges D A, Jackson H G, Saleh R A. Analysis and design of digital integrated circuits in deep submicron technology [ M ]. Is. 1. ] :[s.n. ] ,2005.
  • 8Ker K D, Chen T Y, Wu C Y. ESD protection design on analog pin with very low input capacitance for high-frequency current -mode application [ J ]. IEEE Solid - State Circuits, 2000,35 (8) :1194-1199.
  • 9陈裕妮,贾新章,张德胜,等.微电子器件试验方法和程序[s].北京:总装备部军标出版发行部,2005.
  • 10李锟,陈裕妮,秦国林,等.合格制造厂认证用半导体集成电路通用规范[s].北京:总装备部军标出版发行部,2011.

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