低抖动的480 MHz CMOS电荷泵式锁相环

本文设计了一款用于USB2.0时钟发生作用的低抖动、低功耗电荷泵式锁相环电路。其电路结构包含鉴频/鉴相器、电荷泵、环路滤波器、压控振荡器和分频器。电路设计是基于CSM0.18μmCMOS工艺,经HSPICE仿真表明,锁相环输出480MHz时钟的峰峰值抖动仅为5.01ps,功耗仅为8.3mW。

This paper presents a low noise、low power charge pump phase locked loop which is used as clock generator for USB2.0,The active circuit was implemented in CSM 0.18um CMOS technology.The whole PLL consists of phase/frequency detector、charge pump、loop filter、voltage control oscillator and frequency divider.Simulation result shows that,when output frequency is 480MHz,PLL peak to peak jitter is only 5.01ps and power consume is only 8.3mW.