基于CPLD多功能数字钟的优化设计

Optimization Design of Multiple Functional Digital Clock Based on CPLD

针对CPLD设计优化的问题,研究了如何在系统级及模块级对电路进行优化。通过系统级采用精简输入输出电路结构和模块级采用资源共享,逻辑优化等方法在CPLD芯片EPM7128SLC84-15上实现一个带有清零和校时的数字钟。综合之后,使用了112个LC,占总资源的87%,硬件电路运行稳定准确。

This paper introduces the optimization design of CPLD,especially in the system level and the module level.A multiplier function digital clock based on the chip EPM7128SLC84-15 is realized by simplifying the architecture of inputs and outputs circuits in system level as well as optimizing the modules in module level.After synthesis,it is avail of 112 LCs,occupies 87% of the whole source.The hardware circuit runs steady and accurately.