摘要
在深亚微米工艺时代,线间串扰限制了片上互连总线的传输速率,增加了功耗,同时也影响了传输可靠性。针对基于存储转发路由策略的片上网络,采用一个统一编码框架,将不等能力保护码与串扰避免码进行联合设计,以得到高速、可靠和低功耗的片上总线编码方案。通过采用SMIC0.13μmCMOS工艺的仿真结果表明,在同等可靠性要求下,对10mm32bit并行总线采用联合编码方案与未编码方案相比,可以获得38.25%的功耗改善和1.589倍的速度提升。
In the era of deep sub-micron process, inter-wire crosstalk greatly limits the data transmission rate, increases the power consumption and the susceptibility to errors. According to store-and-forward routing strategy based network-on-chip (NoC) , this paper applied a unified coding framework, and proposed a bus coding scheme which was based on joint une- qual error protection (UEP) code and crosstalk avoidance code to achieve a high speed, reliable and low power consumption on-chip connecting. When applied to a 10mm 32-bit parallel bus in SMIC 0.13 μm CMOS technology without any loss in reliability, the simulation results show that the proposed scheme has 38.25% power consumption improvement and a 1. 589 speed-up over the uncoded bus.
出处
《重庆邮电大学学报(自然科学版)》
北大核心
2010年第5期612-617,共6页
Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)
基金
国家"863"计划项目(2007AA01Z291)
教育部博士点新教师基金(200806141015)~~