基于CPLD的虚拟示波器的设计

Design of Virtual Oscillograph Based on CPLD

介绍了一种基于CPLD的高速虚拟示波器的设计,包括数据采集、数据传输和数据处理等部分。本设计使用高速模数转换芯片(ADC)进行高速采样;使用高性能的可编程逻辑器件(CPLD)实现高速数字电路的控制;使用高速大容量存储器(RAM)实时保存采样数据,保证了仪器的高性能。

This paper introduces a design of high-speed data acquisition virtual oscillograph based on CPLD,including data acquisition,transferring and processing.The virtual oscillograph used a high speed Analog to Digital Converters（ADC） to sample at high speed and a high-performance programmable logic device（CPLD） to realize the control of the digital circuit at high speed and a high-speed large capacity memory（RAM）to keep the data of sampling in real time,this has achieved the high performance of the instrument.