基于FPGA的同步时钟报文检测电路的设计

Design of Synchrnous Packet Detection Circuit Based on FPGA

时钟同步技术是解决基于网络的分布式测控系统完成同步测控任务的关键技术,IEEE-1588协议是一种应用于分布式测量和控制系统中的精准时钟同步协议。提出了一种基于IEEE-1588协议在以太网物理层和MAC层之间的介质无关接口(MII/RMII)处检测同步报文的策略和实现精确时间标记方案[1],在此硬件支持方案和方法的基础之上,充分利用FPGA宏模块资源采用较为简便实用的方法设计实现了同步报文检测电路,该部分电路的设计是采用硬件时间标记方案实现IEEE1588高精度时钟同步的基础。在QuartsII 7.2平台下对设计电路进行优化综合和时序仿真,通过在线实时检测验证了电路设计的正确性。初步验证结果表明设计达到课题要求,应用性能良好。

Clock synchronization technology is a key technology for solving web-based and distributed measurement and control systems completing the synchronous testing.IEEE-1588 protocol is a precision clock synchronization agreement applied in distributed measurement and control systems,.A detecting and time-stamping strategy based on IEEE-1588 for Synchronous Packet in Media Independent Interface（MII） is proposed[1].On the basis of the hardware-supporting proposition and method,the detection circuit was designed through making full use of macro blocks within FPGA resources;.This part of the circuit is the basis for achieving IEEE-1588 high precision clock synchronization with a hardware time-stamping program.In QuartsII 7.2 platform,the circuit was optimized and timing-simulated,and the correctness was verified through on-line and real-time detection.The initial validation results shows that the design meets the subject requirements and has a good application performance.