基于FPGA双通道高速数据采集系统的设计与实现

Design and Implementation of Data Acquisition System Based on FPGA

在高性能数据采集系统的设计中,经常遇到两个问题:高采样率情况下,因串扰严重使采样数据不可靠;对输入信号幅度的自适应需要额外硬件开销,增大系统的复杂性;该设计以FPGA器件XC3S500E为核心,选用数据采集芯片MAX12529进行高速双路同步采样,配置MicroBlaze处理器管理各模块,构成一个双通道高速实时数据采集系统;在FPGA内部实现delta-sigma算法的DAC,实现增益实时控制;在采样率为100Msps时,ADC所有位数均有效;系统从合理端接、码型选择和差分时钟等技术细节方面解决了以上问题。

We usually encounter two kinds of problems in the design of high-performance data acquisition system： First,the sampled data are unreliable in the case of high sampling rate due to the serious crosstalk;second,the adaptation to the amplitude of the input signal needs additional hardware overhead and increases the complexity of the system.This design centers on the FPGA device XC3S500E,chooses ADC MAX12529 for high-speed synchronous sampling and configures processor MicroBlaze to manage all the units.The DAC implemented with delta-sigma algorithm in the FPGA,can control gain real-time.In the case of 100 Msps sampling rate,all the ADC＇s bits are available.System solves the above problems from impedance matching,code-type selection,differential clock and other technical details.