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冗余金属对互连线电容特性的影响 被引量:1

Influence of dummy fill on interconnect capacitance
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摘要 在深亚微米尺寸的集成电路设计中,可制造性设计变得越来越重要。从180 nm时代开始,铜互连代替铝已成为趋势,但是铜在制造工程中难刻蚀,因此在工业上引入了化学机械研磨。为了使化学机械研磨取得好的平坦化效果,必须预先改善设计,对版图金属布局进行冗余金属填充,使之满足工艺生产要求。因此,对版图金属布局进行冗余金属填充,成为研究的热点。文章研究了冗余金属的各种因素对互连线电容特性的影响,并在此基础上给出了优化的冗余金属填充方案。 For advanced interconnect technologies with sub-micron dimensions,design for manufacturability(DFM) has become more and more important.Since the beginning of 180 nm era,copper metallization has replaced traditional aluminum technology in the interconnect technology,but it is hard to be eroded,so the chemical-mechanical polishing(CMP) is brought in.In order to achieve chemical-mechanical planarization,it is necessary to amend the design beforehead and insert dummy fill into low-density layout regions to meet the requirement of manufacture,which has become a popular research issue nowadays.In this paper,the influence of dummy fill on interconnect capacitance is analyzed with the variations of possible factors,and based on it,the optimized design for dummy fill is proposed.
出处 《合肥工业大学学报(自然科学版)》 CAS CSCD 北大核心 2010年第11期1721-1724,共4页 Journal of Hefei University of Technology:Natural Science
基金 国家"十一五"重大专项资金资助项目(1Z2008ZX01035-001-08)
关键词 可制造性设计 化学机械研磨 冗余金属填充 耦合电容 design for manufacturability(DFM) chemical-mechanical polishing(CMP) dummy fill coupling capacitance
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参考文献9

  • 1Kahng A B. Design challenges at 65 nm and beyond[C]// Design, Automation & Test in Europe Conf and Exhibition,2007:1-2.
  • 2Steigerwald J M,Murarka S P,Gutmann R J. Chemical mechanical planarization of microelectronic materials [M]. New York : Wiley, 1997 : 5- 7.
  • 3Lee K Y,Wang T C,Chao K Y. Post-routing redundant via insertion and line end extension with via density eonsideration[C]//Proc of ICCAD, 2006 : 633- 640.
  • 4Kahng A B, Samadi K, Sharma P. Study of floating fill impact on interconnect capacitance[C].//Tth International Symposium on Quality Electronic Design, 2006 : 691 - 696.
  • 5Tichy J, Levert J A, Shah L, et al. Conlact mechanics and lubrication hydrodynamics of chemical mechanical polishing [J]. Journal of the Electrochemical Society, 1999, 146 (4) : 1523-1528.
  • 6TsuchiyaA,Onodera H. Effect of dummy fills on high-frequency characteristics of on-chip interconnects [C]//IEEE Workshop on Signal Propagation on Interconnects, 2006: 275-278.
  • 7Kima Y, Petranovicb D, Sylvestera D. Simple and accurate models for capacitance increment due to metal fill insertion [C]//ASPDAC' 07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference, 2007:456 -461.
  • 8王沛东,郭炜,谢憬.集成电路设计中利用填充金属优化压降的方法[J].电子技术(上海),2008,0(6):67-69. 被引量:1
  • 9He Lei, Kahng A B, Tam K H, et al. Variability-driven considerations in the design of integrate&circuit global interconnects[C]//Proc Int VLSI/ULSI Multilevel Inter connection Conf, 2004 : 214- 221.

二级参考文献10

  • 1Ali,I.et al."Chemical Mechanical Polishing of Interlayer Dieletric:A Review,". Solid State Technology . 1994
  • 2Chen,Y.et al."Area Fill Synthesis for Uniform Layout Density,". IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems . 2002
  • 3Stine,B.E.et al."The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes,". IEEE Transactions on Electron Devices . 1998
  • 4SPIDER:Simultaneous Post-Layout IR-Drop and Metal Density Enhancement with Redundant Fill. ICCAD‘05 . Nov.6-102005
  • 5Ajami,A.H."Analysis of IR-drop scaling with implications for deep submicron P/G network designs". Quality Electronic Design . 2003
  • 6Dong-Soo Cho."Efficient modeling techniques for IR drop analysis in ASIC designs". ASIC/SOC Conference . 1999
  • 7Dubey,A."P/G pad placement optimization: problem formulation for best IR drop". Quality of Electronic Design . 2005
  • 8Wang,C-Y."Maximization of power dissipation in large CMOS circuits considering spurious transitions". Circuits and SystemsⅠ . 2000
  • 9Shi-Hao Chen."DFM/DFY practices during physical designs for timing,signal integrity, and power". Design Automation Conference, 2007.ASP-DAC‘07.Asia and South Pacific . 2007
  • 10Shi-Hao Chen."Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits". Design Automation Conference,2007.ASP-DAC ‘07.Asia and South Pacific . 2007

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