摘要
本文介绍了复接系统中数字定时提取电路的原理和结构,分析了数字定时提取电路输出定时的抖动特性,包括抖动幅度和抖动频率。同时,本文还分析了数字定时提取在数字复接系统中的应用,以及其对复接系统性能的影响。
This paper introduces the theory and structure of digital clock extracting circuit in multiplexing system,and analyzes digital clock extracting circuit's jitter performance including jitter amplitude and jitter frequency.Then the paper analyzes the application of digital clock extractor in digital multiplexing system and the influence on the jitter performance of multiplexing system,and presents the results of experiment.
出处
《通信学报》
EI
CSCD
北大核心
1999年第6期91-96,共6页
Journal on Communications