LDPC码offset BP-Based译码算法研究与硬件实现

Studies on offset BP decoding of LDPC codes and its hardware implementation

低密度奇偶校验(Low-Density Parity-Check LDPC)码是一种接近Shannon极限的信道编码,在低信噪比的环境下仍能获得优异的误码率性能,目前应经成为编码界的热点研究课题之一。本文在探讨了LDPC码的经典BP(Belief Propaga-tion)译码算法的基础上,通过分析比较,选取一种复杂度较低,性能较好的offset BP-Based译码算法在FPGA上进行实现,验证了LDPC码的优异性能,对于译码算法的硬件实现具有指导意义。

Low-density parity-check（LDPC）code is a kind of channel code with near Shannon performance, which can achieve outstanding performance even under the low signal to noise ratio, and hence is now a research hotspot in the channel coding field. This paper discusses LDPC code in the classic BP （Belief Propagation） decoding algorithm based on analysis and comparison, finally selects a lower complexity and better performance offset BP-Based decoding algorithm implementation on the FPGA, It verifies the excellent performance of LDPC code, and a guide for hardware implementation.