1.25～3.125Gb/s连续数据速率CDR设计

Design of 1.25-3.125 Gb/s Continuous-Rate CDR Circuits

设计了一款工作速率为1.25~3.125 Gb/s的连续可调时钟数据恢复（CDR）电路,可以满足多种通信标准的设计需求。CDR采用相位插值型双环路结构,使系统可以根据应用需求对抖动抑制和相位跟踪能力独立进行优化。针对低功耗和低噪声的需求,提出一种新型半速率采样判决电路,利用电流共享和节点电容充放电技术,数据速率为3.125 Gb/s时,仅需要消耗50μA电流。芯片采用0.13μm工艺流片验证,面积0.42 mm2,功耗98 mW,测试结果表明,时钟数据恢复电路接收PRBS7序列时,误码率小于10-12。

A continuously variable clock and data recovery（CDR） circuit operating at 1.25-3.125 Gb/s was introduced,which was applicable to the design requirements of various communication standards.The CDR with the phase interpolator based on the dual loop clock could optimize the jitter suppression and phase tracking.A new half-rate sampling and decision circuit was proposed to optimize the low power consumption and low noise.Using a current sharing and node capacitor chargedischarge technique,when the sample rate is 3.125 Gb/s,the current is only 50 μA.The circuit was fabricated in 0.13 μm 1.5/3.3 V CMOS technology.The area is 0.42 mm2,and the power consumption is 98 mW.The test results indicate that the CDR achieves a bit error rate of 10-12 to receive a PRBS7 data at all data rate.