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64位超前进位对数加法器的设计与优化 被引量：3

Design and Optimization of 64-Bit Look-Ahead Logarithmic Adders
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摘要 设计一个应用于高性能微处理器的快速64位超前进位对数加法器。通过分析超前进位对数加法器原理,提出了改进四进制Kogge-Stone树算法的64位超前进位对数加法器结构,并结合使用多米诺动态逻辑、时钟延迟多米诺逻辑和传输门逻辑等技术来设计和优化电路。该加法器采用SMIC 0.18μm CMOS工艺实现,在最坏情况下完成一次加法运算时间为486.1 ps,与相同工艺和相同电路结构采用静态CMOS实现相比,大大减少了加法器各级门的延迟时间,取得良好的电路性能。 A fast 64-bit look-ahead logarithmic adder applying to high-performance microprocessors was designed. By analyzing the look-ahead adder, the 64-bit look-ahead logarithmic adder structure was proposed, which based on the improved radix-4 Kogge-Stone tree algorithm, and combined the domino dynamic logic, clock-delay domino logic and transmission gate to design and optimize the circuit. Using SMIC 0.18 μm CMOS process, in the worst case, the computation time is 486.1 ps, which greatly reduces all levels of the gate delay time and makes a good performance compared with that of the circuit based on the static CMOS with the same process and circuit structure.
作者 王仁平 何明华 陈传东 戴惠明 黄扬国
机构地区 福州大学物理与信息工程学院
出处 《半导体技术》 CAS CSCD 北大核心 2010年第11期1116-1121,共6页 Semiconductor Technology
基金 福建省区域科技重大项目(2009HZ010002) 福建省自然科学基金(重点)(2007J0003) 福建省教育厅(JA09001)
关键词 多米诺动态逻辑 时钟延时多米诺 对数加法器 点操作 Kogge-Stone树 domino dynamic logic clock-delay domino logarithmic adder dot operations KoggeStone tree
分类号 TN432 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

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共引文献3

同被引文献21

  • 1郭天天,张志勇,卢焕章.快速浮点加法器的FPGA实现[J].计算机工程,2005,31(16):202-204. 被引量：7
  • 2吴金,应征.高速浮点乘法器设计[J].电路与系统学报,2005,10(6):6-11. 被引量：7
  • 3徐东明.实现快速乘法的几种改进贝斯算法[J].西安邮电学院学报,2006,11(1):61-65. 被引量：3
  • 4李明,曹家麟,冉峰,马世伟.基于流水线的自检测进位相关和加法器设计[J].微电子学与计算机,2006,23(4):48-49. 被引量：2
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  • 9Jin Zhan - peng, Shen Xu - bang, Bai Yong - qiang. A 64 - bit fast adder with 0.18 μm CMOS technology [ C]//Proceedings of IEEE International Symposium on Communications and Information Technologies. Beijing: [ s. n. ], 2005:1 167 -1 171.
  • 10Rabeay J M.数字集成电路一电路、系统与设计[M].周润德,译.北京:清华大学出版社,2008:171-431.

引证文献3

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半导体技术
2010年 第11期

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