摘要
研究了一种全差分高增益、低功耗的CMOS运算放大器,采用折叠共源共栅结构、开关式共模反馈以及宽摆幅偏置电路。基于CSMC 0.6μm CMOS工艺,采用HSPICE软件对电路进行仿真。对各性能参数的仿真结果表明,该电路在输入2.5 V电压的情况下,此电路的开环直流增益为80 dB,相位裕度80°,单位增益带宽74 MHz,具有较高的增益,而且功耗小于2 mW。
Study of a fully differential high-gain,low-power CMOS op-amp,It folded cascode structure,switch-mode common-mode feedback,as well as wide-swing bias circuit.Based on CSMC 0.6 μm CMOS process,using HSPICE circuit simulation software.The various performance parameters of the simulation results show that the circuit in the input voltage of 2.5 V,this circuit is open-loop DC gain of 80 dB,phase margin 80°,the unit-gain bandwidth of 74 MHz,with a high gain,and the power of small 2 mW.
出处
《核电子学与探测技术》
CAS
CSCD
北大核心
2010年第10期1364-1366,共3页
Nuclear Electronics & Detection Technology
关键词
全差分
折叠
共源共栅
高增益
Fully differential
folding
cascode
high-gain
