期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

基于STI工艺的高压LDMOS器件设计与优化 被引量：1

Optimization and design of LDMOS Based on STI Technology
下载PDF
导出
摘要 在LDMOS功率器件设计中可以引入STI工艺替代LOCOS工艺来进一步抑制表面电荷效应,以提高LDOMS功率器件的耐压强度及降低比导通电阻。本文将介绍STI工艺的优势和LDMOS器件设计原理,并在TSMC 0.6μm BCD工艺为基础上增加STI工艺流程来设计一款适用于汽车电子应用的40V LDMOS器件。通过ATHENA(工艺模拟)和ATLAS(器件仿真)仿真实验与器件参数提取,表明采用STI工艺的LDMOS器件比采用LOCOS工艺的LDMOS器件在耐压漂移区长度比方面提高了23.40%,且比导通电阻降低了66.12%。 For suppressing the surface charge effect to obtain higher breakdown voltage and lower Ron,sp,we choose STI technology to replace STI technology.The paper will introduce the superiority of STI technology and the basic principles of LDMOS design,and a 40V LDMOS based on TSMC 0.6um BCD technology added with STI technology will be designed for automotive applications.Using ATHENA and ATLAS to simulate the devices and extract the parameters of LDMOS,the data shows that the LDMOS with STI technology have better performance compare with the LDMOS with LOCOS technology,for the breakdown voltage VS the length of drift increased 23.4% and the decreased 66.12%.
作者 周杰 陈利 郭东辉
机构地区 厦门大学物理系 厦门大学电子工程系
出处 《中国集成电路》 2010年第12期46-52,共7页 China lntegrated Circuit
关键词 LDMOS STI工艺 高压器件 LDMOS STI High-voltage device
分类号 TN386 [电子电信—物理电子学]
  • 相关文献

参考文献14

  • 1JoneF.Chen, J.R.Lee, Kuo-Ming Huang, C.M.Liu. Mechanism and Tsung-Yi Improvement On-Resistance Degradation Induced by Avalanche Breakdown in Lateral DMOS Transistors[J]. IEEE Trans Elec dev, 2008,55 ( 8 ) :2259-2262.
  • 2Hamza Yilmaz. Optimication and Surface Charge Sensitivity of High-voltage Blocking Stuctures with Shallow Junctions [J]. IEEE trans.Electron Devices, 1991, 38 ( 7 ) :1666-1675.
  • 3Zahir Parpia, C.ANDRE T. SALAMA. Optimization Of RESURF LDMOS Transistors: An Analytical Approach [J].IEEE Trans Elec Dev, 1990, 37 ( 3 ) : 789-796.
  • 4AndrewB. Kahng, Puneet Sharma. Exploiting STI Stress for Performance. IEEE International Conference, 2007,Nov :83-90.
  • 5Ke-Wei Su, Yi-Ming sheu. A Scaleable Model for STI Mechanical Stress Effect on Layout Dependence of MOS Electrical Characteristics. IEEE Conference , Custom Integrated Circuits Conference,2003:245-248.
  • 6V. P. O' Neil and P. G. Alonas, "Relation between oxide thickness and the breakdown voltage of a planar junction with field relief electrode," IEEE Trans. Electron Devices, vol. Ed-26, pp. 1098-1100.
  • 7Mayank Shrivastava ,Maryam Shojaei Baghini. Part Ⅰ: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices. IEEE Trans Dev,2010, 57 ( 2 ) :448-457.
  • 8Ru-Yi Su, P. Y. Chiang, the Initial Hot-Carrier Jeng Gong. Investigation on Injection in P-LDMOS Transistors With Shallow Trench Isolation Structure.IEEE Trans Dev,2008,55 ( 2 ) :3569-3573.
  • 9Appels J A , Vaes H M J .High voltage thin layer devices ( RESURF devices ) [A]. IEDM Tech Dig[C]. 1979,25 ( 3 ) :238-241.
  • 10C. T. Huang, Bing-Yue Tsui.The Impact of Hing-Vohage Drift N-Well and Shallow Trench Isolation Layouts on Electrical Characteristics of LDMOSFETS. IEEE 2007.

二级参考文献15

  • 1吴秀龙,陈军宁,孟坚,高珊,柯导明.SOI LDMOS晶体管耐压结构的研究[J].半导体技术,2005,30(3):27-31. 被引量：4
  • 2卢豫曾.高压RESURF　LDMOSFET的实现[J].电子学报,1995,23(8):10-14. 被引量：6
  • 3Parpia Z,Ander C,Salama T.Optimization of RESURF analytical LDMOS transistors:an approach[J].IEEE Trans Elec Dev,1990,37(3):789-796.
  • 4Sankara E M,Narayanan,Amaratunga G,et al.A study of the resurf principle for thin epitaxial layer high voltage integrated circuits[A].Int Symp Power Semicond Dev and IC's[C].Tokyo,Japan.1992.160-175.
  • 5Ludikhuize A W.A review of RESURF technology[A].Int Symp Power Semicond Dev and IC's[C].Toulouse,France.2000.11-18.
  • 6Stengl R,Falck E.Surface breakdown and stability of high-voltage planar junctions[J].IEEE Trans Elec Dev,1991,38(9):2181-2188.
  • 7Yilmaz H.Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions[J].IEEE Trans Elec Dev,1991,38(7):1666-1675.
  • 8Hossain Z,Ishiguro T,Tu L,et al.Field-plate effects on the breakdown voltage of an integrated high-voltage LDMOS transistor[A].Int Symp Power Semicond Dev and IC's[C].Kitakyushu,Japan.2004.237-240.
  • 9Appels J A,Vaes H M J.High voltage thin layer devices (RESURF devices)[A].IEDM Tech Dig[C].1979,25(3):238-241.
  • 10Conti F,Conti M.Surface breakdown in silicon planar diodes equipped with field plate[J].Sol Sta Elec,1960,15(2):93-105.

共引文献2

同被引文献7

引证文献1

中国集成电路
2010年 第12期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部