SimTile:片状多核处理器的高效模拟器(英文)

SimTile: An Efficient Simulator of Tiled Chip Multi-processor

传统的基于共享总线的多核芯片随着核心数增加产生了瓶颈问题。新型TiledCMP(chip multiprocessor)的结构设计中,片上核心互联网络对提高扩展能力和执行效率起到了重要作用。为了实现低延迟、高带宽的核心通信,高速点对点网络方式的片上多核互联结构模拟成为研究的热点。抽象片上Tiled方式16核功能单元结构,设计实现了SimTile模拟器,可提供配置灵活、功能单元齐全的片上多核处理器设计,支持高效率的全局共享缓存、高速片上路由结构。模拟器采用模块化的组件配置方式,片上核心数量与互联网络结构、数据一致性协议、全局寄存器通信与cache共享模式等,均可通过精简的参数调整。实验表明模拟器执行效率较高,为片上多核研究提供了灵活、高效并具备可扩展性的新平台。

Traditional bus sharing multi-processor chips meet bottleneck trouble with the number of processor cores increasing. In the structure design of novel Tiled CMP（chip multi-processor）, onchip interconnection shows great impact on platform scalability and performance. Implementation of low latency and high bandwidth onchip routing structure becomes current hotspot. Execute-driven SimTile is implemented by a structure of Tiled 16-core CMP design, which can offer flexible configuration and full-functional CMP building models. The simulator supports efficient global shared cache hierarchy and high performance onchip routing structure. Modules configuration is adopted to setup the platform parameters, such as processor numbers, interconnection network topology, cache coherence protocols, global registers communication and the storage hierarchy etc. The simulator has been evaluated to have fine efficiency in Tiled CMP simulation as to provide a novel flexible and well scalable platform.