基于Verilog的全数字锁相环的设计

The Design of DPLL Based on Verilog

文章介绍了全数字锁相环的基本结构和工作原理,提出了一种基于verilog的全数字锁相环的设计方法,并利用QuartusII6.0软件对设计进行了时序仿真.

In this paper,the basic structure and working principle of ADPLL are introduced firstly.Besides,the method of design of ADPLL based on verilog is put forward.At last,the design of ADPLL is timing simulated with QuartusII6.0 software.