摘要
随着芯片面积的增加及电路复杂性的增强,系统的可靠性逐渐下降.为了保证有较高的可靠性,人们将容错技术引进了集成电路的设计中.文中分析了d-叉树的k-FT结构的可靠性,同时讨论了如何分配冗余单元才能使系统具有较高可靠性的问题.
An increase in chip area and circuit complexity leads to a decrease in the system reliability. In order to get a better reliability, the fault tolerant technique is introduced into the IC design. In this paper, the reliability in k FT architectures of the d ary tree is analysized, and the problem of how to allocate redundant elements in order to make the system have a better reliability is discussed.
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
1999年第2期197-200,共4页
Journal of Xidian University
基金
国防科工委预研基金
国家863计划项目资助