边沿取样电路和同步动态时序电路综合

Edge Samping and Synthesis of Synchranous Dynamic Sequential Circuits

本文提出用电容代替触发器作为记忆元件的双边沿同步动态时序电路（ＳＤＳＣ）的综合方法．基于电路三要素（信号、网络和负载）理论，首先推导出边沿取样定理；接着研究普适双边沿状态图和电路图的关系，再将卡诺图方法由门级发展到元件级；最后提出ＳＤＳＣ的状态编码原则，从而形成有效的ＳＤＳＣ的综合方法，用此方法设计了一些结构极简单的动态电路，诸如错码检测电路仅用２２个ＭＯＳ管，８４２１ＢＣＤ码十进制计数器仅用３１个ＭＯＳ管等．

This paper presents a synthesis of synchronous dynamic sequential circuits (SDSC) in which capacitor is used as memory element instead of flip flop for double edge trigger.On the basis of theory of three essential circuits elements (signal,network and load),the edge sampling theorem is derived first,then a Karnaugh map method is developed from gate stage into element stage and finally the state assignment principle for CDSC is presented,so that an efficient synthetic procedure of SDSC is formed.By the use of the synthetic procedures,we have designed some SDSC which structures are very simplified,such as that the error code detecting circuits consists of only 22 MOS transistors and 8421BCD 10 counter consists of only 31 MOS tramsisters.