准循环LDPC码低存储量译码器设计与实现

Design and implementation of a memory efficient QC-LDPC code decoder

研究了准循环低密度奇偶校验(quasi-cyclic low density parity check,QC-LDPC)码及最小和译码算法,设计了合理的非均匀量化译码方案。充分利用准循环LDPC码校验矩阵的准循环结构特点,设计了一种低存储量准循环LDPC码的译码结构,详细描述各部分组成及功能。基于最小和译码算法及非均匀量化方案,给出了纠错性能的模拟测试结果。按照该译码结构在Xilinx公司的XC3S2000器件上实现了码长为9216、码率为1/2的准循环LDPC码译码器。FPGA(field programmable gate array)实现结果表明,与传统译码结构相比,该译码结构可节省约30%的存储空间,在性能与实现复杂度间取得了较好的平衡。

This paper studied the QC-LDPC （quasi-cyclic low density parity check） codes and min-sum decoding algo-rithm, and designed a proper ununiform decoding scheme for quantization. According to the structure of parity check matrix of QC-LDPC code, a decoder architecture was designed, with its components and function discussed in detail. According the decoding algorithm and quantization scheme, simulated error correcting performance was made. A QC-LDPC decoder was implemented in Xilinx XC3S2000 FPGA （field programmable gate array） , whose codeword length is 9 216 and code rate 1/2. FPGA implementation results show that 30% memory can be reduced compared to the traditional designs, achie- ving better tradeoff between performance and complexity.