2^(2～31)可编程分频器电路的逻辑设计与功能验证

2^(2～31) Programmable Frequency Divider Logic Design and Function Test

分频器在集成电路领域有着很广泛的应用,常作为电路的最基本时钟信号输入。以22～31可编程分频器为例,阐述了分频器电路具体的电路逻辑设计,及形成逻辑后的功能验证。电路输入一个基准时钟,通过译码器来编程,利用多级触发器链,可以输出22～31分频。

Frequency dividers are used widely in the integrated circuit,as the basic clock signal import.Use 22～31 Programmable Frequency Divider to expatiate the logic design,and the function test of the logic design.importing a standard clock,through encoder,and using the chain of the triggers,it can export 22～31 dividable frequency.