摘要
给出了一种基于多相滤波的数字信道化接收机的实现方法,系统的处理带宽为875 MHz,解决了高速ADC与FPGA处理速度之间的矛盾。为了克服信道化接收机的接收盲区,采用信道重叠的方法,连续覆盖瞬时带宽。在信道化处理后接测频模块,可以消除虚假信号的输出和提高测频精度。整个接收机在单片FPGA中实现,能够检测同时到达的两个信号,并实时输出脉冲描述字(PDW),经FPGA时序仿真结果验证了算法模型的正确性和有效性。
A realization method of polyphase filtering channelized receivers is given in this paper. The bandwidth of the system is 875 MHz. This method resolves the contradiction between the high-speed ADC and low-speed digital signal processor （FPGA）. In order to eliminate the dead zoon of the receiver, a method to overlap the adjacent channels is adopted to continuously cover the instantaneous bandwidth. The false signal output can be eliminated and frequency-measurement accuracy can be highly improved by connecting the frequency-measurement module after channelized processing. The design can be applied to single chip FPGA. It can deal with both real-time signals which arrive at the time and implement the real-time output of corresponding PDW. -The correctness and the validity of the algorithm model are proved by the placing-and-routing simulation results.
出处
《现代电子技术》
2010年第23期95-98,共4页
Modern Electronics Technique
关键词
数字信道化接收机
多相滤波
参数估计
FPGA
digital channelizing receiver
polyphase filtering
parameter estimation
FPGA
