摘要
为了产生语音调度系统中数据接收端异步接收PCM30/32路一次群串行数据流所需同步时钟的目的,采用以分频计数器为基础模块,辅以相位校正和误校正处理模块从已知速率PCM数据流中提取同步时钟信号的方法,利用可编程逻辑器件和Verilog HDL硬件描述语言对该方法进行实现和仿真验证。结果表明该方法能够有效地利用已有串行数据流产生具备合适相位的同步采样时钟信号。
A method which is based on frequency dividing counter with the assist of phase adjustment and mis-adjustment procedure module, is adopted to develop the synchronous clock from a serial PCM data stream for its receiver in voice dispatching systems. The method＇s implementation and timing simulation result by using CPLD and Verilog HDL are given, which indicate that the method can effectively produce the synchronous clock from a given serial data stream.
出处
《现代电子技术》
2010年第23期192-194,共3页
Modern Electronics Technique
