期刊文献+

基于博弈论的片上总线仲裁机制研究 被引量:2

The Research on the Game Theory-Based On-Chip-Bus Arbitration Mechanism
下载PDF
导出
摘要 随着半导体工艺技术的发展,芯片内部集成的功能模块越来越多.各功能模块通过总线方式连接,因而片上总线仲裁架构成为制约芯片性能提高的瓶颈.通过改善片上总线仲裁器设计,能有效缓解由于各功能模块争用总线资源而引起的芯片性能下降.本文提出一种基于博弈论的片上总线仲裁机制,利用求解多人博弈问题的方法解决总线争用问题,并以片上系统的性能指标为约束条件,得到解决总线争用问题的一般模型.最后,通过仿真及实际硬件平台对算法进行测试,结果表明应用本算法的指令处理速度比应用固定优先级算法快236%,比应用轮换算法快53%. With the development of semiconductor technology,more and more functional modules are integrated on a chip.The on-chip-bus Arbitration architecture has become bottlenecks in the improvement of chip performance,as modules are connected through the bus.The degradation of chip performance due to the contention for bus resources can be relieved by optimizing the design of the on-chip-bus arbiter,so this paper presents a game theory-based on-chip-bus arbitration mechanism which solves the bus contention problem by using game theory.Moreover,we build a general model to solve the problem with restriction of the performance of system on chip.Finally,we test the algorithm through simulation and hardware platform designed by us.Results show that the command processing speed using game theory arbitration is 236% faster than the one using FP(Fixed-Priority) algorithm and 53% faster than the one using RR(Round Robin) algorithm.
出处 《电子学报》 EI CAS CSCD 北大核心 2010年第11期2476-2481,共6页 Acta Electronica Sinica
基金 国家自然科学基金(No.60871059)
关键词 博弈论 仲裁器 片上总线 game theory arbiter on-chip-bus
  • 相关文献

参考文献12

  • 1熊志辉,李思昆,陈吉华,王海力,边计年.一种基于层次平台的SoC系统设计方法[J].电子学报,2004,32(11):1815-1819. 被引量:9
  • 2郎荣玲,戴冠中.集成电路的模块生成与选择算法[J].电子学报,2005,33(11):1955-1958. 被引量:2
  • 3黄凯,殷燎,林锋毅,葛海通,严晓浪.一种多处理器原型及其系统芯片设计方法[J].电子学报,2009,37(2):305-311. 被引量:6
  • 4Kanishka lahiri,Anand Raghunathan.Power analysis of system-level on-chip communication architectures.Hardware/Software Codesign and System Synthesis,2004.CODES+ISSS 2004.International Conference on.Stockholm,Sweden,2004 September 8-10.236-241.
  • 5Davies A C.Dynamic properties of a multiway arbiter.IEEE International Symposium on Circuits and Systems.Geneva,Switzerland,2000 May 28-31,221-224.
  • 6Thomas B Preuber,Martin Zabel,Rainer G Spallek.About carriers and tokens re-using adder circuits for arbitration.IEEE International Conference on Signal Processing,Systems Design and Implementation.Athens,Greece,2005 November 2-4.59-64.
  • 7Yan Zhang.Architecture and performance comparison of a statistic-based lottery Arbiter for shared bus on chip[J].IEEE Transactions on Consumer Electronics,2005,51(1):1313-1316.
  • 8Si Qing Zheng,Mei Yang.Algorighm-hardware codesign of fast parallel round-robin arbiters[J].IEEE Transactions on Parallel And Distributed Systems.2007,18(1):84-94.
  • 9Schelling Thomas.The Strategy of Conflict[M].Boston:Harvard University Press:1980.
  • 10Robert Gibbons.Game Theory for Applied Economists[M].New Jersey:Princeton University Press,1992.

二级参考文献35

  • 1A A Jerraya, et al. Special Issue on MPSoC[J].IEEE Computer,2005,38(7) :36 - 40.
  • 2Grant Martin. Overview of the MPSoC Design Challenge[A]. 43th DAC[C]. New York: ACM,2006. 274 - 279.
  • 3Ahmed Jerraya, Wayne Wolf. Multiprocessor Systems-on-Chip [M]. San Francisco: Elsevier Morgan Kaufmann, 2005.11 - 13.
  • 4Keutzer K et al. System-level design: Orthogonalization of concerns and platform-based design[J]. IEEE Transaction On CAD of Integrated Circuits and Systems, 2000,19( 12):1523- 1543.
  • 5D D Gajski, J Zhu, R Domer, A Gerstlauer, S Zhao. SpecC: Specification language and Methodology [ M ]. Boston: Kluwer Academic Publishers, 2000.25 - 78.
  • 6CoWare, SoC platform-based design using Convergen SC/SystemC[EB/OL], 2002, http://www.coware. com.
  • 7Mentor Graphics, Seamless CVE[EB/OL], http://www. mentor. com/products/fv/hwsw_coverification/seamless/.
  • 8Xilinx, System Generator for DSP Performing Hardware-in-the-Loop With the Spartan? -3E Starter Kit EDB/OL]. www. xilinx. corn/products/boards/s3 estarter/files/s3esk_ sysgen_ hw_ in_ loop. pdf.
  • 9Altera, DSP Builder [ DB/OL ]. www. altera. com. cn/ products/software/products/dsp/dsp- builder. html.
  • 10ARM, ARM Integrator CP Baseboard [DB/OL ]. http:// www. arm. com/documentation.

共引文献13

同被引文献28

  • 1Jerraya A A and Wolf W. Multiprocessor Systems-on-Chips[M]. San Francisco: Morgan Kaufmanns Publishers Incorporated, 2005: 1-18.
  • 2Shanthi D and Amutha R. Design of efficient on-chip communication architecture in MpSoC[C]. 2011 International Conference on Recent Trends in Information Technology (ICRTIT). Chennai, 2011: 364-369.
  • 3Jakob L, Martin L, and Thomas P. A robust asynchronous interfacing scheme with four-phase dual-rail coding[C]. International Conference on Application of Concurrency to System Design (ACSD), Hamburg, 2012: 122-131.
  • 4Lahiri K, Raghunathan A, and Lakshminarayana G. The LOTTERYBUS on-chip communication architecture[J]. IEEE Transactions on Very Large Scale Integration (VLS1) Systems, 2006, 14(6): 596-608.
  • 5Peng Huan-kal and Lin Youn-long. An optimal warning- zone-length assignment algorithm for real-time and multiple- QoS on-chip bus arbitration[J]. ACM Transactions on Embedded Computing Systems, 2010, 9(4): 1-5.
  • 6Parsan F A, A1-Assadi W K, and Smith S C. Gate mapping automation for asynchronous NULL convention logic circuits]J]. IEEE Transactions on Very Large Scale Integration ( VL S1) Systems, 2014, 22(1): 99-112.
  • 7Pons J F, Brault J J, and Savaria Y. An FPGA compatible asynchronous wake-up receiver for wireless sensor networks[C]. 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS 2012), Montreal, 2012: 373-376.
  • 8Smith S C. Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits[J]. IEEE Transactions on Very Large Scale Integration (VLS1) Systems, 2007, 15(6): 672-683.
  • 9Min J J, Lee Y L, and Wu S S. Model-driven design and generation of new multi-facet arbiters: from the design model to the hardware synthesis[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(8): 1184-1196.
  • 10Shanthi D and Amutha R. Performance analysis of on-chip communication architecture in MPSoC[C]. 2011 International Conference on Emerging Trends in Electrical and Computer Technology (ICETECT), Tamil Nadu, 2011: 811-815.

引证文献2

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部