期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

一种2.5Gb/s带预加重结构的低压差分串行发送器 被引量：4

A 2.5Gbit/s Low Voltage Differential Signal Transceiver with Pre-Emphasis
下载PDF
导出
摘要 设计了一种带预加重结构的低压差分信号(LVDS)串行发送器,改进了传统LVDS发送器的共模电平反馈控制结构。LVDS串行发送器采用双运放反馈控制电路,在避免集成大电阻的同时,能够更好地稳定差分信号的输出摆幅。采用电路预加重技术,克服了数据高速传输过程中的高频信号损失问题。基于0.25μm CMOS工艺,实现了LVDS发送器,芯片面积约为0.03mm2,可满足2.5 Gb/s的高速串行数据传输。 A low-voltage differential signal（LVDS）serial transceiver was designed with improved closed-loop feedback control structure and pre-emphasis.Using this circuit,output common-mode voltage could be controlled without large resistance.A pre-emphasis circuit was employed to overcome high frequency signal loss during transmission.Designed and implemented in 0.25 μm CMOS process,the transceiver,which occupies a chip area of 0.03 mm2,is applicable for 2.5 Gbit/s serial data transmission.
作者 韦雪明 李平
机构地区 电子科技大学电子薄膜与集成器件国家重点实验室
出处 《微电子学》 CAS CSCD 北大核心 2010年第6期770-773,共4页 Microelectronics
关键词 串行发送器 低压差分信号 预加重 Serial transceiver Low voltage different signal（LVDS） Pre-emphasis
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献6

  • 1IEEE standard for low voltage differential signals(LVDS) for scalable coherent interface[S]. IEEE Std 1596. 3- 1996, 1996.
  • 2张家川,刘伯安.高速多电平LVDS收发器设计[J].微电子学与计算机,2007,24(4):69-71. 被引量：8
  • 3ZHAO Zhenyu, WANG Jianjun, LI Shaoqing, et al. A 2. 5-Gb/s 0. 13um CMOS current mode logic transceiver with pre-emphasis and equalization [C] // 7th Int Conf ASIC. Guilin,China. 2007. 368-371.
  • 4叶菁华,陈一辉,郭淦,洪志良.一种适用于高速串行数据通信的发送器[J].Journal of Semiconductors,2003,24(7):763-768. 被引量：3
  • 5PAUL W,DICKSON T O,VOINIGESCU S P. A 1.5 V 20/30 Gbps CMOS backplane driver with digital preemphasis[C] // Proc IEEE Cust Integr Circ Conf. Orlando,Florida,USA. 2004: 23-26.
  • 6CHOI S W, LEE H B, PARK H J. A three-data differential signaling over four conductors with pre-emphasis "and equalization: a CMOS current mode implementation [J]. IEEE J Sol Sta Circ, 2006, 41 (3) : 633-641.

二级参考文献12

  • 1王中伟,张盛兵,沈戈,赵勇.一种在电路SOC验证接口设计方法研究[J].微电子学与计算机,2005,22(9):68-70. 被引量：3
  • 2Le Fevre A,Flett R. A 100Mb/s muhi-LAN crosspoint chipset for cable management. IEEE J Solid-State Circuit, 1997,32(7) ;1115.
  • 3Lee K,Kim S,Ahn G,et al. A CMOS serial link for fully duplexed data communication. IEEE J Solid-State Circuit, 1995,30(4) :353.
  • 4Specification of Serial ATA/High Speed Serialized AT Attachment, 2000.
  • 5Park C H, Kim B. A low-noise, 900-MHz VCO in 0.6-μmCMOS. IEEE J Solid-State Circuits,1999,34(5):586.
  • 6Chen Yu, Hong Zhiliang. Design of clock multiplier for 2.5 Gbps gigabit Ethernet transceiver.Research and Progress of SSE,to be published
  • 7Chen Yu, Hong Zhiliang, Zhu Jiang. Design of high-performance multiphase clock generator used in LVDS driver with 0.25μm CMOS technology. Chinese Journal of Semiconductors, 2001,22(8):1069(in Chinese)
  • 8Ammar R, Ajouri C. GTL: a low-swing solution for highspeed digital logic. Proceedings of WESCON95,San Francisco,1995.
  • 9Donnelly K S,Chan Y F,Ho J T C,et al. A 660-MB/s interface megacell portable circuit in 0.3-μm-0. 7-μm CMOS ASIC. IEEE J Solid-State Circuits,1996,31(12):1995.
  • 10Boni A,Pierazzi A,Vecchi D.LVDS I/O interface for gb/s-per-pin operation in 0.35μm CMOS[J].IEEE Journal of Solid-State circuits,2001,36(4):260～266

共引文献9

同被引文献39

  • 1黄林,郭淦,叶菁华,陈一辉,洪志良.一种采用半速结构的CMOS串行数据收发器的设计[J].Journal of Semiconductors,2005,26(1):180-186. 被引量：2
  • 2黄震,刘彬.脉冲激光测距中时间间隔测量的新方法[J].光电子．激光,2006,17(9):1153-1155. 被引量：17
  • 3Chen M D, Silva-Martinez J, Nix M, et al. Low-Vohage I.ow-Power LVI)S Drivers [J]. IEEE Journal of Solid-State Circuits, 2005, 40(2): 472-479.
  • 4Yah Y, Szymanski T H. Low Power High Speed I/O Interfaces in 0.18btm CMOS [C]//ICECS2003. Sharjah: IEEE, 2003: 826-829.
  • 5Sun Jiaxing, Ye Qing, Zhou Yumei, et al. Signal Integrity for 0.18t:m CMOS Technology [J]. Chinese Journal of Semiconductors, 2003, 24(10): 1030-1033.
  • 6Rysin A, Livshits P, Sofer S, 2009. Tel Aviv: IEEE, 2009: Interference (ISI) in ()n-die Transmission lanes [C]//COMCAS.
  • 7Stievano I S, Maio I A, Canavero E G, et al. Behavioral Macromodels of Differential Drivers with Pre-emphasis [C]// SPI2005. Garmiseh-Partenkirchen: IEEE, 2005: 129-132.
  • 8Choi S W, Lee H "B, Park H J. A Three-Data I)itferential Signaling over Four Conductors with Pre-Emphasis and Equalization: a CMOS Current Mode Implementation [J] - IEEE Journal of Solid-State Circuits, 2006, 41 (3) : 633-641.
  • 9Djahanshahi H, Hansen F, Salama C A T. Gigabit-per-Second, ECL-Compatible I/O Interface in 0.35-t m CMOS [J]. IEEE Journal of Solid-State Circuits, 1999, 34(8) : 1074-1083.
  • 10Taguchi M, Shi K. Signal Transmission with Reduced Ring of Signals: U.S. Patent, 20(:2/0000847 [P]. 2002-01-03.

引证文献4

二级引证文献27

微电子学
2010年 第6期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部