摘要
设计了一种具有前馈结构的Σ-Δ A/D转换器。运用零点、极点优化技术,使Σ-Δ调制器在具有较高稳定性的同时得到优化的信噪比。调制器采用前馈3阶单环结构,采用1位量化,用全差分开关电容方式实现,时钟频率为256 kHz,信号带宽为1 kHz。电路采用SMIC 0.18μmCMOS工艺,仿真结果表明,Σ-Δ A/D转换器达到的信噪比为90.54 dB,有效位数为14.8位;在3.3 V电源电压下,功耗为5.18 mW。
A Σ-Δ A/D converter with feedforward topology was presented.Both high stability and optimal SNR were achieved for Σ-Δ modulator by using zero and pole optimizations.The modulator,which was based on feedforward third-order single-loop architecture with single-bit output and full-differential switched-capacitor,had a sampling frequency of 256 kHz and signal bandwidth of 1 kHz.Results from simulation based on SMIC's 0.18 μm CMOS technology showed that the Σ-Δ A/D converter achieved an SNR of 90.54 dB and an ENOB of 14.8.The circuit consumes 5.18 mW of power from a 3.3 V supply.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第6期774-777,781,共5页
Microelectronics