低功耗可配置FFT处理器的ASIC设计

ASIC Design of Low Power and Reconfigurable FFT Processor

提出了一种低功耗可配置FFT处理器的设计方案和存储器地址产生方法,可进行8点、16点、32点、64点、128点和256点运算。采用基2算法和基于存储器的顺序结构,将长位宽的存储器分成两个短位宽的存储器,并在蝶形单元中将4个实数乘法器减少为3个,进一步降低了功耗。同时,在存储器读写和蝶形单元的运算之间采用流水线结构,以提高处理速度。该FFT处理器采用SMIC 0.18μm CMOS工艺库进行综合及布局布线,芯片核心面积为1.09 mm2,功耗仅为0.69 mW/MHz,实现了低功耗的目标。

A low power and reconfigurable FFT processor was designed and memory address generation algorithm was presented.This processor could be scaled for 8-,16-,32-,64-,128-and 256-point computation.Radix-2 algorithm and sequential structure based on memory were employed in this design.A long-bit memory was divided into two short-bit memories,and the number of real multiplications in butterfly was decreased from 4 to 3 to further reduce power consumption.The design was synthesized,placed and routed using SMIC 0.18 μm CMOS process library.The circuit occupies a chip area of 1.62 mm2,and its power consumption is only 0.69 mW/MHz,which reached the low power target.