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一种10位160MS/s采样保持电路的设计 被引量：2

Design of a 1.8V 10-Bit 160MS/s CMOS Sample-and-Hold Circuit
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摘要 设计了一种用于流水线型A/D转换器的10位160 MS/s CMOS采样保持器。电路采用电容翻转式结构,以及运用增益提高技术(gain-boosting)的折叠式共源共栅放大器,以满足高速、高精度的要求;优化采样电容和运算放大器指标,以保证噪声容限和线性指标;优化辅助运放,从而保证运放的稳定性。HSPICE仿真结果表明,在78.83 MHz输入信号、160.34 MHz工作频率下,输出信号的无杂散动态范围为77.3 dB。 A 10-bit 160 MS/s sample-and-hold circuit for pipelined A/D converter was designed and fabricated in 1.8 V 0.18-μm CMOS process.In this circuit,flip-around SHA and gain-boosting folded cascode OTA were used to achieve high speed and high resolution.The sampling capacitor and OTA were optimized to obtain sufficient noise tolerance and linearity.Gain-boosting amplifier was carefully designed to ensure stability of the OTA.HSPICE simulation showed that,for input signal of 78.83 MHz,the proposed SHA had an SFDR of 77.3 dB at a sampling frequency of 160.34 MHz.
作者 龙善丽 白涛 唐兴刚 张紫乾
机构地区 华东光电集成器件研究所
出处 《微电子学》 CAS CSCD 北大核心 2010年第6期792-795,共4页 Microelectronics
关键词 采样保持电路 电荷重分配 折叠式共源共栅放大器 Sample-and-hold circuit Charge redistribution Folded cascode OTA
分类号 TN432 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

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二级参考文献6

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共引文献8

同被引文献11

  • 1谭珺,唐长文,闵昊.一种100MHz采样频率C MOS采样/保持电路[J].微电子学,2006,36(1):90-93. 被引量：9
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  • 3VAN DE VEL H, BUTER B, VAN DER PLOEG H, et al. A 1.2-V 250-mW 14-b 100 MS/s digitally calibrated pipeline ADC in 90-nm CMOS [J]. IEEE J Sol Sta Circ, 2009, 44(4): 1047-1059.
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  • 5YANGW, KELLY D, MEHR I, et al. A 3 V 340 mW 14 h 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist [J]. IEEE J Sol Sta Circ, 2001, 36(12):1931-1936.
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  • 10YANG J F, LI Z Y. Design and error analysis of a OTA for high speed pipeline ADC [C]//IEEE 5th Int Symp MAPE. Chengdu, China. 2013: 679-683.

引证文献2

二级引证文献3

微电子学
2010年 第6期

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