一种存储器低功耗优化方法及其应用

A Low-Power Optimization Method for Memory and Its Application

根据在特定的VLSI系统中存储器读写地址以自然顺序连续变化为主的特点,提出一种基于折叠与数据打包的结构变换方法,通过减少存储器访问次数实现功耗优化。在SMIC 0.13μm工艺条件下进行分析,结果表明:该方法以较小的面积开销,即可使功耗降低约50%。基于此方法进行优化,设计了一种适用于CMMB系统的低功耗LDPC译码器。分析表明,在面积仅分别增大1.2%和6.0%的前提下,该LDPC译码器功耗分别降低21%和33%。

A low-power optimization method for memory was proposed based on folding structure and data packaging.In a given VLSI system,when read and write addresses of the memory changes mainly in accordance with the natural order,the proposed method could be used to realize low-power optimization by reducing memory access.Analysis based on SMIC 0.13 μm process showed that power consumption of the memory was reduced by about 50% only at the expense of a small area.Based on this method,a low power LDPC decoder was designed for CMMB system.It has been demonstrated that power consumption of the LDPC decoder was reduced by 21% and 33% with only 1.2% and 6.0% area increase,respectively.