星载FPGA混合时钟域设计

Design of multiple clocks in FPGA for spacecraft

设计了以XC2V3000为核心处理芯片的星载FPGA系统的涵盖高速、中速、低速和甚低速的混合时钟域,对混合时钟域可靠性设计中的关键问题,如资源降额、时序冗余、布局布线等,做了深入研究,提出了基于全局时钟网络、时钟鉴相、FIFO缓冲的多时钟同步设计解决方案,并在实际工程中验证了方案的可行性和可靠性。

This paper describes the design and implementation of multiple clocks in a spacecraft, using XC2V3000 as main processor, including high speed, medium speed, low speed and very low speed clocks. After plenty of research in the key points, such as source derating, sequence redundancy, plan and mute, a fine resolution based on global clock networks, phase demodulation, FIFO memories is proposed, and finally used in later project. Implementation of synchronous system with multiple clocks proves that the proposed resuhion is available and reliablel.