期刊文献+

InSb红外焦平面探测器结构应力的ANSYS分析 被引量:21

STRESS IN InSb INFRARED FOCAL PLANE ARRAY DETECTOR ANALYZED WITH ANSYS
下载PDF
导出
摘要 借助有限元软件系统分析了铟柱取不同直径时红外探测器整体结构的应力分布.模拟结果表明,在固定铟柱高度的前提下,当铟柱直径以2μm的步长从36μm减小到18μm的过程中,InSb芯片上的最大应力值呈现出先减小,后线性增加的趋势,但铟柱上应力最大值始终保持在15.7MPa左右,且分布几乎不变.S i读出电路上的应力小于InSb芯片上的应力值,变化趋势类同于InSb芯片上应力的变化趋势.铟柱直径取30μm时,InSb芯片和S i读出电路上的应力均达到最小值260MPa和140MPa,整个器件的应力分布在接触区呈现明显的集中性、均匀性,分布更合理. Based on viscoplastic Anand model,von Mises stress distribution of the infrared focal plane array detector is analyzed by finite element method.Simulation results show that as the diameters of the indium bump decreases from 36μm to 18μm in step of 2μm,the maximum stress existing in InSb chip reduces at first,then increases linearly with indium bump diameters.Yet the stress distribution in the indium bump is almost unchangeable and its maximum value keeps at 15.7MPa.Furthermore the maximum stress in Si-CMOS readout integrated circuit is smaller than that of InSb chip,and its changing tendency chart is almost the same as that of InSb chip.When the diameter of the indium bump is set to 30μm,the maximum stresses existing in both InSb chip and Si CMOS readout integrated circuit reach the minimal value 260MPa and 140MPa,respectively.Simulations also show that the stress distribution at the contact areas is uniform and concentrated,the stress value in the whole infrared focal plane array detector is smallest,and its distribution is promising.
出处 《红外与毫米波学报》 SCIE EI CAS CSCD 北大核心 2010年第6期431-434,共4页 Journal of Infrared and Millimeter Waves
基金 国家自然科学基金资助项日(60904023)
关键词 ANSYS 焦平面 INSB 结构应力 ANSYS focal plane array InSb structural stress
  • 相关文献

参考文献10

  • 1陈伯良,孙维国,梁平治,郑志伟,王正官,朱晓池,江美玲,龚启兵,丁瑞军,黄水安.InSb凝视红外焦平面组件研制和应用[J].红外与激光工程,2002,31(5):419-423. 被引量:19
  • 2皋利利,薛松柏,张亮,盛重.FCBGA元器件焊点可靠性的有限元分析[J].焊接学报,2008,29(8):73-76. 被引量:6
  • 3彩霞,陈柳,张群,徐步陆,黄卫东,谢晓明,程兆年.倒扣芯片连接焊点的热疲劳失效[J].Journal of Semiconductors,2002,23(6):660-667. 被引量:7
  • 4刘士龙,秦连城,杨道国,郝秀云.固化残余应力对倒装焊器件热-机械可靠性的影响[J].电子元件与材料,2003,22(2):44-47. 被引量:2
  • 5Wang G Z.,Cheng Z N.,Becke K R,et al.Applying Anand model to represent the viscoplastic deformation behavior of solder alloys[J].Journal of Electronic Packaging,2001,123(3):247-253.
  • 6Wilde J,Becker K,Thoben M,et al.Rate dependent constitutive relations based on Anand model for 92.5Pb5Sn2.5Ag solder[J].IEEE Transactions on Advanced Packaging,2000,23(3):408-414.
  • 7Chang R W,Patrick Mccluskey F.Constitutive relations of indium in extreme-temperature electronic packaging based on Anand model[J].Journal of Electronic Materials,2009,38(9):1855-1859.
  • 8Kim S,Ledbetter H.Low-temperature elastic coefficients of polycrystalline indium[J].Materials Science and Engineering A,1998,252(1):139-143.
  • 9Hermida E B,Melo D G,Aguiar J C,et al.Temperature dependence of the viscoelastic response of In,Sn and In-Sn alloys[J].Journal of Alloys and Compounds,2000,310(1):91-96.
  • 10Reed R P,Mc Cowan C N,Walsh R P.Tensile strength and ductility of indium[J].Materials Science and Engineering,1988,102(2):227-236.

二级参考文献30

  • 1况延香,朱颂春.SMT中的先进微电子封装技术概况[J].电子工艺技术,2004,25(4):178-182. 被引量:1
  • 2薛松柏,胡永芳,禹胜林.BGA封装器件焊点抗剪强度的试验[J].焊接学报,2005,26(10):62-64. 被引量:5
  • 3陆飞.FCBGA器件PCB组装应用的若干要点[J].电子工艺技术,2006,27(2):87-90. 被引量:3
  • 4陈伯良.64×64元混成InSb焦平面原型器件研制进展.第十二届全国红外科学技术交流会论文集[M].上海,1996.194.
  • 5Suhir E.The future of microelectronics and photonics and the role of mechanics and materials.ASME J Electronic Packaging,1998,120:1
  • 6Lau J H.Solder joint reliability of flip chip and plastic ballgrid array assemblies under thermal,mechanical,and vibrational conditions.IEEE Trans Comp Packag,Manufact Technol,1996,19:728
  • 7Doi K,Hirano N,Okada T,et al.Prediction of thermal fa-tigue life for encapsulated flip-chip interconnection.The International Journal of Microcircuits and Electronic Packaging,1996,19(3):231
  • 8Nysather J B,Lundstr o¨ m P,Liu J.Measurements of solder bump lifetime as a function of underfill material properties.IEEE Trans Comp,Packag,Manufact Technol,1998,21:281
  • 9Gektin V,Bar-Cohen A,Ames J.Coffin-Manson fatigue model of underfilled flip-chip.IEEE Trans Comp,Packag,Manufact Technol,1997,20(3):317
  • 10Madenci E,Shkarayev S,Mahajan R.Potential failure sites in a flip chip package with and without underfill.ASME J Electron Packag,1998,120:336

共引文献28

同被引文献127

引证文献21

二级引证文献29

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部