基于FPGA的RS译码器的设计与实现

Design and Implementation of RS Decoder Based on FPGA

针对Reed-Solomon(RS)码译码过程复杂、译码速度慢和专用译码器价格高等问题,以联合信息分发系统终端J系列报文信息位采用的RS(31,15)码为例,介绍了基于改进的无求逆运算的Berlekamp-Massey(BM)迭代算法的RS译码原理,采用Verilog硬件描述语言对译码器中各个子模块进行了设计,并基于现场可编程门阵列平台,在QuartusII6.0环境下进行了仿真,验证了RS译码器的纠错能力,实现了参数化与模块化的RS译码器设计。

For the problems as complex RS decoding process,low decoding speed and expensive specific RS decoder,and with RS（31,15） code adopted by JTIDS terminal as an example,the RS decoding theory based on the improved no-inversion BM iteration algorithm is described.With FPGA platform and Verilog HDL,the submodules of the RS decoder are designed.The correction ability of the RS decoder is simulated and verified with the software of Quartus II 6.0.And the parameterized and modularized design of RS decoder is thus achieved.