基于FPGA的记忆多项式数字预失真器的实现

FPGA Implementation of MP Digital Predistortion Linearizers

介绍了一种基于FPGA的记忆多项式数字预失真器的实现。首先,通过间接学习结构采用LMS算法提取记忆多项式系数;其次,变换记忆多项式的形式,构造易于FPGA实现的基于查找表(LUT)的预失真单元;最后给出了顶层模块图及实验结果,结果充分表明了该预失真器的有效性。

This paper describes the implementation of FPGA-based memory polynomial predistorter.Firstly,the coefficients of memory polynomial are extracted by using LMS algorithm with indirect learning structure;Secondly,transform the form of polynomial to construct LUT-based predistortion unit;Finally,the top-level block diagram are represented and the effectiveness of the predistortion linearizers are demonstrated by experimental results obtained in a real platform.