采用可复位延迟链形成无谐波、快速锁定的延迟锁相环

A Delay-locked Loop with Harmonic-free and Fast-locking Based on Resettable Delay Line

为提高锁定速度,一种带单步复位(RES)延迟链的全数位延迟锁相环(ADDLL)得以发展。随着新的可复位技术的发展,DLL快速锁定和无谐波的特点逐渐显现。主要在常见的DLL电路中加入可复位延迟链,采用SI MC 180 nmCOMS工艺,并采用Synopsys的HSI M仿真器对电路进行仿真。仿真结果显示,改进的DLL工作频率范围可达50～250 MHz,锁定时间明显减小,且无谐波信号。

An all digital delay-locked loop（ADDLL） with ＂reset in every step＂（RES） delay line is developed in order to reduce the locking time.Due to the novel resettable mechanism of delay line,the DLL has the property of fast-locking and harmonic-free.According to the simulation results in SMIC 180 nm CMOS technology,the proposed delay-locked loop（DLL） can cover the operating range from 50～250 MHz.